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A31W65132 seri es preliminary lcd controller - driver preliminary (february, 2001, version 0.1) amic technology, inc. document title lcd controller - driver revision history rev. no. history issue date remark 0.0 initial issue april 20, 2000 preliminary 0.1 error correction: february 19, 2001 c3 - ? c3+ c1+ ? c1 - c1 - ? c1+ c2 - ? c2+ c2+ ? c2 - add pad coordinates change power supply range: 2.0v to 5.5v ? 2.4v to 5.5v
A31W65132 seri es preliminary lcd controller - driver preliminary (february, 2001, version 0.1) 1 amic technology, inc features n power supply range : 2.4v to 5.5v 6.0v to 16.5v (lcd drive) n internal lcd drivers : 132 segment signal drivers 65 commons signal drivers n power save current (<1ua) n on chip 132 x 65 display data ram n 8 bit 80/68 - series parallel interface ,serial interface n build - in rc oscillator or external clock input n 1:7 / 1:9 bias ratio n 64 level internal contrast control n 8 level internal resistor ratio set (v5 voltage) n build - in tem perature compensation circuit n internal bias divider circuit n on chip internal dc/dc converter / external power supply n dual/ triple/ quad booster n internal icon common output system for indicators n tcp package, gold bumps the A31W65132 seri es is a cmos lcd driver, which has 132 segment, and 65 common graphic display. it has 80/68 - series 8 bit parallel and serial interface capability for operating with general cpu. the internal 65 x 132 display data ram makes the display of both graphics and characters possible. besides the general lcd driver features, it has on chip lcd bias divider circuit such that minimize external component required in system application.
A31W65132 series preliminary (february, 2001, version 0.1) 2 amic technology, inc block diagram 1. block overview page address register start line register & counter oscillating circuit lcd timing circuit power on reset display ram 8580 bits page address decode start line address decoder data latch column address decoder line control start line register lcd driver data input/ output column address register & counter display data control mpu interface for 68-series & 80-series c1- command decoder a0 p/s c68/80 cs2 r/w e lcd power supply circuit status register c1+ c2+ c2- v out v cnt vrs irs v 1 to v 5 vdd d0 to d7 vss cominc1 com1 to 64 seg1 to 132 cls cl c3+ hpm frs fr dof m/s res cs1 cominc2
A31W65132 series preliminary (february, 2001, version 0.1) 3 amic technology, inc block diagram 2. lcd power supply ci rcuit block diagram quad booster, triple booster & double booster reference voltage voltage regular reference regular adjustment circuit bias resister voltage follower command register v4 v3 v2 v1 v5 v out v cnt c3+ c1- c1+ c2+ clk c2- irs vrs hpm
A31W65132 series preliminary (february, 2001, version 0.1) 4 amic technology, inc pad assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 287 266 265 83 nc frs fr cl dof nc vss cs1 cs2 vdd res a0 vss wr,r/w rd, e vdd d0 d1 d2 d3 d4 d5 d6, scl d7, si nc vdd vdd vdd vdd vss vss vss vss vss vss vss nc v out v out c3+ c3+ nc com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 com15 com14 com13 com12 nc cominc2 com64 com63 com62 com61 com60 com59 com58 com57 com56 com55 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 nc nc com44 com43 com42 com41 com40 com39 . pad pitch segment driver 65um comon driver 65um control pad 100um . gold bump size drive 43x85um input pin 73x85um . gold bump height 18um (typ.) chip identification marks (the identification marks are larger than the actual scaling) (the identification marks are made of ai patterns) unit : um com38 com37 com36 com35 com34 com33 seg132 seg131 seg130 seg129 c1- c1- c1+ c1+ c2+ c2+ c2- c2- vss vss vrs vrs vdd vdd v1 v1 v2 v2 nc v3 v3 v4 v4 v5 v5 nc v cnt v cnt vdd vdd vdd m/s cls vss c68/80 p/s vdd hpm vss irs vdd nc 106 nc nc com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 cominc1 seg1 seg2 seg3 seg4 105 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 50 50 50 50 50 50 50
A31W65132 series preliminary (february, 2001, version 0.1) 5 amic technology, inc pad coordinates unit: m m (the origin is the center of the chip) no. pin name x y no. pin name x y 1 nc - 5152.5 - 910 49 c2 - 1684.4 - 910 2 frs - 4971.2 - 910 50 vss 1784.4 - 910 3 fr - 4706 - 910 51 vss 1884.4 - 910 4 cl - 4445.8 - 910 52 vrs 1984.4 - 910 5 dof - 4180.6 - 910 53 vrs 2084.4 - 910 6 nc - 3999.3 - 910 54 vdd 2184.4 - 910 7 vss - 3899.3 - 910 55 vdd 2284.4 - 910 8 cs1 - 3785.7 - 910 56 v1 2384.4 - 910 9 cs 2 - 3685.7 - 910 57 v1 2484.4 - 910 10 vdd - 3572.7 - 910 58 v2 2584.4 - 910 11 res - 3459.7 - 910 59 v2 2684.4 - 910 12 a0 - 3359.7 - 910 60 nc 2784.4 - 910 13 vss - 3246.7 - 910 61 v3 2884.4 - 910 14 w/r , r/ w - 3133.7 - 910 62 v3 2984.4 - 910 15 rd , e - 3033.7 - 910 63 v4 3084.4 - 910 16 vdd - 2920.7 - 910 64 v4 3184.4 - 910 17 d0 - 2739.1 - 910 65 v5 3284.4 - 910 18 d1 - 2473.9 - 910 66 v5 3384.4 - 910 19 d2 - 2213.7 - 910 67 nc 3484.4 - 910 20 d3 - 1948.1 - 910 68 v cnt 3584.4 - 9 10 21 d4 - 1687.9 - 910 69 v cnt 3684.4 - 910 22 d5 - 1422.7 - 910 70 vdd 3784.4 - 910 23 d6, scl - 1162.5 - 910 71 vdd 3884.4 - 910 24 d7, si - 896.9 - 910 72 vdd 3984.4 - 910 25 nc - 715.6 - 910 73 m/s 4097.4 - 910 26 vdd - 615.6 - 910 74 cls 4197.4 - 910 27 vdd - 515.6 - 910 75 vss 4310. 4 - 910 28 vdd - 415.6 - 910 76 c68/80 4423.4 - 910 29 vdd - 315.6 - 910 77 p/s 4523.4 - 910 30 vss - 215.6 - 910 78 vdd 4636.4 - 910 31 vss - 115.6 - 910 79 hpm 4736.4 - 910 32 vss - 15.6 - 910 80 vss 4836.4 - 910 33 vss 84.4 - 910 81 irs 4936.4 - 910 34 vss 184.4 - 910 82 vdd 5036.4 - 910 35 vss 284.4 - 910 83 nc 5136.4 - 910 36 vss 384.4 - 910 84 nc 5146.5 - 726.3 37 nc 484.4 - 910 85 com32 5146.5 - 661.3 38 v out 584.4 - 910 86 com31 5146.5 - 596.3 39 v out 684.4 - 910 87 com30 5146.5 - 531.3 40 c3+ 784.4 - 910 88 com29 5146.5 - 466.3 41 c3+ 8 84.4 - 910 89 com28 5146.5 401.3 42 c1 - 984.4 - 910 90 com27 5146.5 - 336.3 43 c1 - 1084.4 - 910 91 com26 5146.5 - 271.3 44 c1+ 1184.4 - 910 92 com25 5146.5 - 206.3 45 c1+ 1284.4 - 910 93 com24 5146.5 - 141.3 46 c2+ 1384.4 - 910 94 com23 5146.5 - 76.3 47 c2+ 1484.4 - 910 95 com22 5 146.5 - 11.3 48 c2 - 1584.4 - 910 96 com21 5146.5 53.7
A31W65132 series preliminary (february, 2001, version 0.1) 6 amic technology, inc pad coordinates (continued) unit: m m (the origin is the center of the chip) no. pin name x y no. pin name x y 97 com20 5146.5 118.7 145 seg26 2632.5 910 98 com19 5146.5 183.7 146 seg27 2567.5 910 99 com18 5 146.5 248.7 147 seg28 2502.5 910 100 com17 5146.5 313.7 148 seg29 2437.5 910 101 com16 5146.5 378.7 149 seg30 2372.5 910 102 com15 5146.5 443.7 150 seg31 2307.5 910 103 com14 5146.5 508.7 151 seg32 2242.5 910 104 com13 5146.5 573.7 152 seg33 2177.5 910 105 com12 5146.5 638.7 153 se g34 2112.5 910 106 nc 5167.5 910 154 seg35 2047.5 910 107 nc 5102.5 910 155 seg36 1982.5 910 108 com11 5037.5 910 156 seg37 1917.5 910 109 com10 4972.5 910 157 seg38 1852.5 910 110 com9 4907.5 910 158 seg39 1787.5 910 111 com8 4842.5 910 159 seg40 1722.5 910 112 com7 4777.5 910 160 s eg41 1657.5 910 113 com6 4712.5 910 161 seg42 1592.5 910 114 com5 4647.5 910 162 seg43 1527.5 910 115 com4 4582.5 910 163 seg44 1462.5 910 116 com3 4517.5 910 164 seg45 1397.5 910 117 com2 4452.5 910 165 seg46 1332.5 910 118 com1 4387.5 910 166 seg47 1267.5 910 119 cominc1 4322.5 9 10 167 seg48 1202.5 910 120 seg1 4257.5 910 168 seg49 1137.5 910 121 seg2 4192.5 910 169 seg50 1072.5 910 122 seg3 4127.5 910 170 seg51 1007.5 910 123 seg4 4062.5 910 171 seg52 942.5 910 124 seg5 3997.5 910 172 seg53 877.5 910 125 seg6 3932.5 910 173 seg54 812.5 910 126 seg7 3867.5 9 10 174 seg55 747.5 910 127 seg8 3802.5 910 175 seg56 682.5 910 128 seg9 3737.5 910 176 seg57 617.5 910 129 seg10 3672.5 910 177 seg58 552.5 910 130 seg11 3607.5 910 178 seg59 487.5 910 131 seg12 3542.5 910 179 seg60 422.5 910 132 seg13 3477.5 910 180 seg61 357.5 910 133 seg14 3412.5 910 181 seg62 292.5 910 134 seg15 3347.5 910 182 seg63 227.5 910 135 seg16 3282.5 910 183 seg64 162.5 910 136 seg17 3217.5 910 184 seg65 97.5 910 137 seg18 3152.5 910 185 seg66 32.5 910 138 seg19 3087.5 910 186 seg67 - 32.5 910 139 seg20 3022.5 910 187 seg68 - 97.5 910 140 seg21 2957.5 910 188 seg69 - 162.5 910 141 seg22 2892.5 910 189 seg70 - 227.5 910 142 seg23 2827.5 910 190 seg71 - 292.5 910 143 seg24 2762.5 910 191 seg72 - 357.5 910 144 seg25 2697.5 910 192 seg73 - 422.5 910
A31W65132 series preliminary (february, 2001, version 0.1) 7 amic technology, inc pad coordinates (continued) unit: m m (the origin is the center of the chip) no. pin name x y no. pin name x y 193 seg74 - 487.5 910 241 seg122 - 3607.5 910 194 seg75 - 552.5 910 242 seg123 - 3672.5 910 195 seg76 - 617.5 910 243 seg124 - 3737.5 910 196 seg77 - 682.5 910 244 seg125 - 3802.5 910 197 seg78 - 747.5 910 245 seg126 - 3867.5 910 198 seg79 - 812.5 910 246 seg127 - 3932.5 910 199 seg80 - 877.5 910 247 seg128 - 3997.5 910 200 seg81 - 942.5 910 248 seg129 - 4062.5 910 201 seg82 - 1007.5 910 249 seg130 - 4127.5 910 202 seg83 - 1072.5 910 250 seg131 - 4192.5 910 203 seg84 - 1137.5 910 251 seg132 - 4257.5 910 204 seg85 - 1202.5 910 252 com33 - 4322. 5 910 205 seg86 - 1267.5 910 253 com34 - 4387.5 910 206 seg87 - 1332.5 910 254 com35 - 4452.5 910 207 seg88 - 1397.5 910 255 com36 - 4517.5 910 208 seg89 - 1462.5 910 256 com37 - 4582.5 910 209 seg90 - 1527.5 910 257 com38 - 4647.5 910 210 seg91 - 1592.5 910 258 com39 - 4712.5 910 211 seg92 - 1 657.5 910 259 com40 - 4777.5 910 212 seg93 - 1722.5 910 260 com41 - 4842.5 910 213 seg94 - 1787.5 910 261 com42 - 4907.5 910 214 seg95 - 1852.5 910 262 com43 - 4972.5 910 215 seg96 - 1917.5 910 263 com44 - 5037.5 910 216 seg97 - 1982.5 910 264 nc - 5102.5 910 217 seg98 - 2047.5 910 265 nc - 516 7.5 910 218 seg99 - 2112.5 910 266 com45 - 5146.5 638.7 219 seg100 - 2177.5 910 267 com46 - 5146.5 573.7 220 seg101 - 2242.5 910 268 com47 - 5146.5 508.7 221 seg102 - 2307.5 910 269 com48 - 5146.5 443.7 222 seg103 - 2372.5 910 270 com49 - 5146.5 378.7 223 seg104 - 2437.5 910 271 com50 - 5146 .5 313.7 224 seg105 - 2502.5 910 272 com51 - 5146.5 248.7 225 seg106 - 2567.5 910 273 com52 - 5146.5 183.7 226 seg107 - 2632.5 910 274 com53 - 5146.5 118.7 227 seg108 - 2697.5 910 275 com54 - 5146.5 53.7 228 seg109 - 2762.5 910 276 com55 - 5146.5 - 11.3 229 seg110 - 2827.5 910 277 com56 - 514 6.5 - 76.3 230 seg111 - 2892.5 910 278 com57 - 5146.5 - 141.3 231 seg112 - 2957.5 910 279 com58 - 5146.5 - 206.3 232 seg113 - 3022.5 910 280 com59 - 5146.5 - 271.3 233 seg114 - 3087.5 910 281 com60 - 5146.5 - 336.3 234 seg115 - 3152.5 910 282 com61 - 5146.5 - 401.3 235 seg116 - 3217.5 910 283 com 62 - 5146.5 - 466.3 236 seg117 - 3282.5 910 284 com63 - 5146.5 - 531.3 237 seg118 - 3347.5 910 285 com64 - 5146.5 - 596.3 238 seg119 - 3412.5 910 286 cominc2 - 5146.5 - 661.3 239 seg120 - 3477.5 910 287 nc - 5146.5 - 726.3 240 seg121 - 3542.5 910
A31W65132 series preliminary (february, 2001, version 0.1) 8 amic technology, inc input/output pin function pin no . symbol type description 7, 13, 30 - 36, 50 - 51, 75, 80 vss supply ground 10, 16, 26 - 29, 54 - 55, 70 - 72, 78, 82 vdd supply power supply pin 52 - 53 vrs supply external vreg voltage supply for lcd voltage regulator. 74 cls inpu t cls = high : internal oscillator is enabled cls = low : internal oscillator is disabled display clock input m/s cls cl h h output h l input l h input l l input 4 cl in/out the cl pins must be connected in master/slav e mode. m/s = high : master mode m/s = low : slave mode m/s cls power supply circuit oscillator circuit cl fr dof frs h h enable enable output output output output h l enable disable input output output ou tput l h disable disable input input input output l l disable disable input input input output 73 m/s input the signals fr, dof , cl of slave chips must be supplied from the master chip. 3 fr in/out lc alternating current signal pin m/s = high : output m/s = low : input the fr pins must be connected in master/slave mode. 5 dof in/out lcd blanking control pin m/s = high : output m/s = low : input the dof pins must be connected in master/slave mode 2 frs output the frs output for the static icon drive and is used in conjunction with the fr pin, one of the static icon electrodes is connected to the fr pin, and the other is connected to frs pin.
A31W65132 series preliminary (february, 2001, version 0.1) 9 amic technology, inc input/output pin function (continued) pin no. sy mbol type description 81 irs input the irs is used in v5 voltage adjustment irs = high : used the internal resistors irs = low : used the external resistors this pin is used in master mode. when in slave mode, it can fixed to either high or low level 79 hpm input hpm = high : normal mode power supply hpm = low : high power mode power supply this pin is used in master mode. when in slave mode, it can fixed to either high or low level 8, 9 cs1 cs2 input chip select input. when cs1 = low, cs2 = high, enable the chip select 11 res input reset pin, low enable 12 a0 input a0=low: command input. a0=high: display data input and outputs 68 - series r/ w =high: read, r/ w =low : write 1 4 r/ w ( wr ) input 80 - series : write enable, active low 68 - series : enable clock signa l input, active high 15 e ( rd ) input 80 - series : read enable, active low 77 p/s input parallel/serial interface select input high : 8 - bit parallel interface low : serial interface , display data ram reading is not supported 76 c68/80 input microprocessor interfa ce select input high : 68 - series interface is selected low : 80 - series interface is selected 17 - 24 d0 - 7 (si, scl) input/ output 8bit bi - directional data bus to be connected to microprocessor?s data bus p/s = high : 8 - bit configuration data bus connection p/s = low : serial interface connection d6 serial data input scl d7 serial clock input si 120 - 251 seg1 - seg132 output provide the lcd segment driving signal 85 - 105, 108 - 118, 252 - 263, 266 - 285 com1 - com64 output provide the lcd common driving signal 11 9, 286 cominc1 cominc2 output provide the icon common driving signal, the same signal is output in master/slave mode 38 - 39 v out output boosting voltage output 40 - 41 c3+ input 3rd - step boosting capacitor negative connection
A31W65132 series preliminary (february, 2001, version 0.1) 10 amic technology, inc input/output pin function (c ontinued) pin no. symbol type description 46 - 47 c2+ input 2nd - step boosting capacitor negative connection 48 - 49 c2 - input 2nd - step boosting capacitor positive connection 44 - 45 c1+ input 1 st - step boosting capacitor negative connection 42 - 43 c1 - input 1 st - step boosting capacitor positive connection 68 - 69 v cnt input external lcd power regulator voltage control through a resistive voltage divider. irs = low: these can be used, because the internal resistors are disabled. irs = high: these can not be use d. 56 - 57 v1 input 58 - 59 v2 input 61 - 62 v3 input 63 - 64 v4 input 65 - 66 v5 input lcd driver bias voltage. they can be supplied externally or generated by the internal bias divider. 1: 7 bias 1: 9 bias v1 1/7 x v5 1/9 x v5 v2 2/7 x v5 2/9 x v5 v3 5/7 x v5 7/9 x v5 v4 6/7 x v5 8/9 x v5 ? inputs lcd drive bias voltage when using an external lcd power supp ly circuit. v5 3 v4, v3, v2, v1 > vss 1, 6, 25, 37, 60, 67, 83 - 84 , 106 - 107, 264 - 265, 287 nc open no connection
A31W65132 series preliminary (february, 2001, version 0.1) 11 amic technology, inc commands table bit pattern command a0 e r/ w d7 d6 d5 d4 d3 d2 d1 d0 comment set display on/off 0 1 0 1 0 1 0 1 1 1 0 1 d0:0 display off: display goes out, regardless of the content of the display data ram d0:1 display on: normal display set display start line 0 1 0 0 1 displa y start line address (0 - 63) sets the line address of the display data ram output to com1 page address set 0 1 0 1 0 1 1 page address (0 - 8) sets the page address of the display data ram. page 8 is assigned to the icon display upper 4 bits of column addres s set 0 1 0 0 0 0 1 upper 4 bits of column address sets upper 4 bits of the display data ram column address lower 4 bits of the column address set 0 1 0 0 0 0 0 lower 4 bits of the column address lower 4 bits of display data ram column address status rea d 0 0 1 status status read display data write 1 1 0 write data in display data ram writes data of d0 to d7 in the display data ram display data read 1 0 1 read data from display data ram reads data from d0 to d7 from the display data ram adc select 0 1 0 1 0 1 0 0 0 0 0 1 reverses upper or lower display data ram column address d0:0 normal: column addresses 00 to 83h correspond to segment outputs 1 to 132 d0:1 reverse: column addresses 00 to 83h correspond to segment outputs 132 to 1 display normal/ re verse 0 1 0 1 0 1 0 0 1 1 0 1 d0:0 normal : ?1? makes the display be lit d0:1 reverse : ?0? makes the display be lit the icon display is not reversed display all - lit on/off 0 1 0 1 0 1 0 0 1 0 0 1 d0:0 normal display d0:1 display all - lit on common output sequence select 0 1 0 1 1 0 0 0 1 * * * d3:0 in a normal order com1 to com64 d3:1 in a reverse order com64 to com1 read modify write 0 1 0 1 1 1 0 0 0 0 0 increments display data ram column address only during writing end 0 1 0 1 1 1 0 1 1 1 0 read modify write release. d2:0 normal display (default) d2:1 icon only display boosting control data: icon only display 0 1 0 1 1 0 1 1 0 1 boosting control data d1 d0: 00 01 10 11 f osc f osc /2 f osc /4 (default) f osc /8
A31W65132 series preliminary (february, 2001, version 0.1) 12 amic technology, inc commands ta ble (continued) bit pattern command a0 e r/ w d7 d6 d5 d4 d3 d2 d1 d0 comment reset 0 1 0 1 1 1 0 0 0 1 0 it does not affect the contents of the display data ram. after resetting, display starts according to the reset value: 1.rese ts the display start line register to the 1st line. 2.resets the column address counter to address 0. 3. resets the page address counter to page 0. 4.turns off the read modify write. 5.static icon off, static icon display register off. d1, d0 = 0, 0 6.commo n output sequence in normal order 7.v5 voltage regulator internal resistor ratio set mode clear. d2~d0 = 1, 0, 0 8.lcd voltage command fine adjustment data d5~d0 = 1, 0, 0, 0, 0, 0 bias selection 0 1 0 1 0 1 0 0 0 1 0 1 d0 = 0 : 1/9 bias selection (defaul t) d0 = 1 : 1/7 bias selection power supply circuit operation control 0 1 0 0 0 1 0 1 control mode lcd power supply circuit operation mode select lcd voltage command 0 1 0 1 0 0 0 0 0 0 1 the lcd voltage command fine adjustment data must set after the lcd voltage command set lcd voltage command fine adjustment data * * 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 minimum value maximum value (total 64 level) v5 voltage regulator internal resistor ratio 0 1 0 0 0 1 0 0 0 . 1 0 . 1 0 . 1 small large voltage regulator internal resistor (ra/rb) ratio, total 8 level static icon display command set 0 1 0 1 0 1 0 1 1 0 0 1 static icon display command set : d0 = 0 static icon display off d0 = 1 static icon display on (the static icon disp lay register set command must set after the static icon display on command set) static icon display register set (double byte command) * * * * * * mode static icon display register set : d1 d0 = 0 0 :off 0 1 : blinking , one s econd intervals 1 0 : blinking , 0.5 second intervals 1 1 : on reference voltage temperature coefficient select 0 1 0 1 1 1 0 0 1 0 1 0 1 d0 : 0 0.05%/ c (default) d0 : 1 0.2%/ c d1 : 0 internal vreg (default) d1 : 1 external vreg power save set display off then set display all - lit on command nop 0 1 0 1 1 1 0 0 0 1 1 non operation command
A31W65132 series preliminary (february, 2001, version 0.1) 13 amic technology, inc operation of lcd display driver 1. powering on setting sequence recommended command setting sequence: (1) set display off : in order to prevent unnecessary characters from being displayed during powering on of the power . when the master is turned on, the oscillator circuit is operable immediately. after the powering on, it will be in all - off state. (2) set display all - lit off: normal display operation. (3) set lcd power supply operation control (4) set bias select: 1. bias selection setting 2. v5 voltage regulator internal resistor ratio setting 3. lcd voltage command and lcd voltage command fine adjustment data setting (5) set reference voltage temperature compensation coefficient (6) end command input (7) adc select setting (8) set display normal/reverse: d0 : 0 normal display data "1" makes the display be lit . d0 : 1 reverse display data "0" makes the display be lit. (9) set display start line address: changing the display start line allows for page change on the display screen as well as vertical smooth scroll. (10) set common output sequence (11) icon onl y display (12) static icon display select (13) display data write: after writing the display data, the column address is automatically incremented. to write the display data in succession after setting the 1st column address to be written by the column ad dress setting command, the column address is not needed to be set each time. the icon display data is valid for only d0. write ?l? or data to be displayed in all display data ram before turning the display on. (14) display on 2. set powering off, power save mode set powering off sequence : (1) set display off (2) set display all - lit on (3) set lcd power supply circuit off power save mode : the power save mode has two modes, one is sleep mode and the other is standby mode. the mpu is still able to access the display data ram when in power save mode. combination of commands state display on display all - lit off normal display operation display on display all - lit on all - lit display display off display all - lit off aii - off static icon display on display off display all - lit on standby mode (power save) static icon display off display off display all - lit on sleep mode (power save)
A31W65132 series preliminary (february, 2001, version 0.1) 14 amic technology, inc when in sleep mode, the command sleeps the system: internal oscillating circuit and lcd power supply circuit are stopped. all lc drive circuit are stopped, the segment and common outputs are fixed at vss level. when in standby mode: internal oscillating circuit continues to operate and lcd power supply circuits are stopped. the duty drive system lc circuits are stopped, the segment and common outputs are fixed at vss level. the static icon drive system continues to operate. when a reset command is set in the standby mode, the lcd system will enter the sleep mode. when using an external power supply circuit, stop the external power supply circuit and float the lcd power supply when the power save mode is started. when using an external bias resistor in order to reduce the current of power save mode, attach a switching transistor which cuts the current flowing through the bias resistor. the lcd blinking control pin dof will output low signal when the power save mode is start. we can use the dof to stop the external power supply. 3. mpu interface select th e parallel 68 - series, 80 - series interface or serial interface can be selected by p/s, c68/80 pin setup: p/s pin c68/80 pin mpu interface l 80 - series interface selected h h 68 - series interface selected l don't care serial interface selected 3.1 mpu parallel 68 - series and 80 - series interface the parallel interface consists of 8 bi - directional data pins (d0 - d7), r/ w ( wr ), a0, e( rd ), cs in order to match the operating frequency of display ram with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. A31W65132 pin name a0 e r/ w cs1 cs2 d0 - d7 68 - series mpu signal a0 e r/ w cs1 cs2 d0 - d7 80 - series mpu signal a0 rd wr cs1 cs2 d0 - d7 3.2 mpu serial interface the seria l interface consists of serial clock input scl, serial data input si and chip select cs1 , cs2, a0. when the serial interface is selected by setting p/s to ?l?, the instruction code is the same as for the parallel interface .by setting cs1 to ?l?, cs2 to ?h?. the serial interface circuit enters an operating state. and by setting cs1 to ?h?, or setting cs2 to ?l?, it will reset the serial interface circuit and initialized the counter. data is input in the order of d7, d6, d5,....d0. the displayed data and commands are written at the rising edge of the scl. the a0 is detected every 8 rising edge of sclk serial clock after the chip select pins is enabled. d7 (si) : serial data input d6 (scl) : s erial clock input d5 to d0 : open a0 : select the command data or display data a0 operation l command write h display data write
A31W65132 series preliminary (february, 2001, version 0.1) 15 amic technology, inc 4. command execution when the input at d0 - d7 is interpreted as a command and it will be decoded and written to the corresponding command register. the user can input the commands continuously without confirming the busy flag of status command register because the command is completely executed within the cycle time (t cyc ) according to the timing charact eristics of the command input. but that re - inputting the command within the executed cycle time is inhibited. the busy flag is outputted to d7 pin with the read instruction, ?h? indicates the chip is in busy state. 5. data bus select when cs1 is held at ?h? level or cs2 is held at ?l? level, the d0 - d7 is in high impedance state. 68/80 - series shared 68 - series 80 - series a0 r/ w e r/ w description 1 1 0 1 reads from display data ram 1 0 1 0 wr ites to display data ram 0 1 0 1 reads status 0 0 1 0 command write to internal register 6. display data ram the display data ram is made of dual port ram. the size of the ram is 64 x 132 + 132 = 8580 bits. write ?l? or data to be displayed in all displa y data ram before turning the display on. 7. accessing the display data ram from mpu in order to match the operating frequency of display data ram with that of the mpu, a dummy read is required before the first actual display data read. when the mpu reads the display data ram, the first dummy read cycle stores the first read data in the bus holder, and then at the next read cycle the mpu read the first read data from the bus holder. it does not need a dummy cycle when mpu writes data to the display data ram. when the mpu write data to display data ram, once the data is stored in the bus holder, then it is written to display data ram before the next data write cycle. 8. set column address (higher, lower nibble) this command specifies the column address (higher an d lower nibble) of the display data ram. the column address will be incremented automatically by each data access after it is pre - set by the mpu. the incrementation of column addresses stops with 83h. 9. set page address (0 - 8) this command positions the page address to 0 of 8 possible positions in display data ram. page 0 - 7 are the graphic display area, and the page 8 are the icon display area. the icon display data is valid for only d0. 10. set display start line (0 - 63) the command is used to change the display page or smooth scroll. with the display start line value equals to 0, d0 of page 0 is mapped to com1. the display start line values of 0 to 63 are assigned to page 0 to 7.
A31W65132 series preliminary (february, 2001, version 0.1) 16 amic technology, inc 11. status read this command shows the status of A31W65132 busy : d7 =0 : the a31w6513 2 is not busy 1 : the A31W65132 is in internal operation or reset state. adc : d6 =0 : adc reverse : column addresses 00 to 7fh correspond to segment outputs 132 to 1. 1 : adc normal : column addresses 00 to 7fh correspond to segment outputs 1 to 132. on/off : d5 =0 : display on 1 : display off reset : d4 =0 : in normal operation state 1 : internal reset operation state psave : d3 =0 : in normal operation state 1 : in power save state icon : d2 =0 : in normal operation s tate 1 : in icon only display state drev : d1 =0 : display normal 1 : display reverse alon : d0 =0 : normal display 1 : display all - lit on 12. common output sequence select output sequence common driving signal output in normal mode common dri ving signal output in reverse mode 1 com1 com64 2 com2 com63 3 com3 com62 . . . . . . 16 com16 com49 17 com17 com48 . . . . . . 63 com63 com2 64 com64 com1 13. icon only display d2 = 0 normal display d2 = 1 icon only display d1 d0 boosting frequenc y 0 0 f osc 0 1 f osc /2 1 0 f osc /4 1 1 f osc /8 when d2=high, regardless of the content of the display data ram, display icon only and lcd panel compelled to be off. when reducing the boosting frequency, the gray scale of icon display differs depending on the panel size or the value of the boosting capacitor. 14. read modify write , end read modify write this command puts the chip in read modify write mode. in this mode the column address is saved before entering the mode, and is incremented by display data wr ite but not by display data read. during the read modify write mode, all commands are usable except the column address set command. end this command relieves the A31W65132 from read modify write mode. the column address that is saved before entering read m odify write mode will be restored.
A31W65132 series preliminary (february, 2001, version 0.1) 17 amic technology, inc 15. rc oscillator circuit the built - in rc oscillator generates the clock for the boosting frequency, and is also used in the display timing. when using the external clock (cls = low or m/s = low), the external clock is inpu t to cl pin. 16. reference voltage temperature compensation coefficient select this command is to set one out of 2 different temperature coefficients in order to match various liquid crystal temperature grades. d v ref = 1 2 1 ref 2 ref t t )i (t iv )i (t iv - - t 2 > t 1 17. the reset circuit after reset by the res pin (low enable), the A31W65132 return to the default status as follows: 1. display off 2. display normal 3. adc select normal 4. power supply circuit operation control d2, d1, d0 = 0, 0, 0 5. serial interface internal counter and register clear 6. lcd power supply bias rate selection = 1/9 7. all indicator lamps - on off (d0 = low) 8. power saving clear 9. v5 voltage regulator internal resistors ra, rb separation 10. turn off the read modify writ e 11. resets the display start line register to 1 st line 12. resets the column address counter to address 0 13. resets the page address counter to page0 14. the seg and com output conditions: seg = v2/v3, com = v1/v4. while res = low, t he cl, fr, frs and dof are fixed to high, and the oscillator and display timing generator stop. the vss level is output from seg and com outputs. 15. static icon off, and static icon display register = off (d1, d0 = 0, 0) 16. common out put sequence in normal order 17. v5 voltage regulator internal resistor ratio set mode clear d2~d0 = 1, 0, 0 18. lcd voltage command fine adjustment data d5~d0 = 1, 0, 0, 0, 0, 0 19. reference voltage temperature coefficient select 0.05%/ c 20. icon only d isplay command: normal display, boosting control d1, d0 = 1, 0 18. lcd power supply circuit the lcd power supply circuit generates the lcd voltage needed for display output, which is controlled by power supply operation control command. it consists of: 1. double / triple / quad dc - dc voltage converter 2. internal resistors and voltage command fine adjustment circuit (64 level) for the v5 voltage regulator 3. lcd bias resistor and voltage follower d2 d1 d0 double/triple/ quad circuit voltage regulator circuit lcd bias r esistor/ voltage follower circuit h l l l h l h l h l h h on off off off on off on off on off on on
A31W65132 series preliminary (february, 2001, version 0.1) 18 amic technology, inc v5= ra + rb ra x vref (v) rb ra vref vss vcnt v5 + - 18.1 double / tripler / quad it is the 2x, 3x , 4x dc - dc voltage converter. please refer to application notes. 18.2 lcd voltage adjustment there are two metho ds of adjusting the lcd voltage as follows: 18.2.1 voltage regulator voltage regulator output v5 is adjusted by internal ra/rb resistors ratio or externally attached ra and rb. vref(v) = (1 - a /162) x vreg vss vout c3+ c1- c1+ c2+ c2- c1 c1 c1 c1 + + vss vout c3+ c1- c1+ c2+ c2- c1 c1 c1 + + + vss vout c3+ c1- c1+ c2+ c2- c1 c1 + + open 4 x step-up voltage circuit 3 x step-up voltage circuit 2 x step-up voltage circuit vdd=3v vss example of booster output double vout = 6v triple vout = 9v quad vout = 12v + +
A31W65132 series preliminary (february, 2001, version 0.1) 19 amic technology, inc temperature coefficient vreg ta = 25 c 0.05%/ c 2.1voltage 0.2%/ c 4.9 voltage external vreg input vrs v5 voltage regulator internal resistor ratio register value and (ra+rb)/ra ratio (for reference) internal resistance ratio register internal (ra+rb)/ra ratio d2 d1 d0 0.05 0.2 vreg ex ternal input 0 0 0 3.0 1.3 1.5 0 0 1 3.5 1.5 2.0 0 1 0 4.0 1.8 2.5 0 1 1 4.5 2.0 3.0 1 0 0 5.0 2.3 3.5 1 0 1 5.5 2.5 4.0 1 1 0 6.0 2.8 4.5 1 1 1 6.4 3.0 5.0 18.2.2 lcd voltage command fine adjustment control software control of 64 volta ge levels ( a ) adjustment of v5 voltage by set 6 bits of the data bus. it can adjust the lcd contrast. lcd voltage command is a two - byte command used as a pair with the lcd voltage command and lcd voltage command fine adjustment control, and both command mu st be issued on after the other. 18.3 static icon display this controls the static drive system display. this is used when one of the static indicator lcd electrodes is connected to the fr terminal, and the other is connected to the frs terminal. the static ico n display command set on is a two - byte command used as a pair with the static icon display command set and static icon display register set. the static icon display command set off is a single byte command. 18.4 lcd bias voltage when use built - in lcd bias resistor, software can control the 1/9, 1/7 bias ratio to match the characteristic of lcd panel. 18.5 voltage follower the voltage follower buffers the lcd bias voltage created by the built - in bias resistor, and supplies it to the lcd drive circuit. 18.6 high power mode when the lcd with large loads, the high power mode power supply (set hpm = low) can improve the quality of the lcd display.
A31W65132 series preliminary (february, 2001, version 0.1) 20 amic technology, inc interface 1. parallel interface 1.1 display data write ( the 80 - series interfa ce) 1.2 display data read (the 80 - series interface) n n+1 n+2 n+3 n+3 n+2 n+1 n r/w data bus holder r/w internal busy flag mp internal timing n x n n+1 r/w data bus holder r/w internal busy flag mp internal timing address set address n dummy read data read address n data read address n+1 n n+1 n+2 n+2 n+1 n x e e column address
A31W65132 series preliminary (february, 2001, version 0.1) 21 amic technology, inc 2 serial interface serial interface display data write timing notes: 1. the user can not reading from A31W65132 when in serial interface mode. 2. a0=high, the data is display data, a0=low, the data is command data. the a0 signal is sampled every 8 th rising edge of scl clock, when the chip becomes active in serial interface mode. 3. the counter and the shift register are reset to the default value when the chip is not active. d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cs1 cs2 si (d7) scl (d6) a0
A31W65132 series preliminary (february, 2001, version 0.1) 22 amic technology, inc display data ram vs ad dress page address page0 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 0, 0, 0, 0 line address d0 d1 d2 d3 d4 d5 d6 d7 page1 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 0, 0, 0, 1 d0 d1 d2 d3 d4 d5 d6 d7 page2 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 0, 0, 1, 0 d0 d1 d2 d3 d4 d5 d6 d7 page3 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h 0, 0, 1, 1 d0 d1 d2 d3 d4 d5 d6 d7 page4 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 0, 1, 0, 0 d0 d1 d2 d3 d4 d5 d6 d7 page5 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h 0, 1, 0, 1 d0 d1 d2 d3 d4 d5 d6 d7 page6 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 0, 1, 1, 0 d0 d1 d2 d3 d4 d5 d6 d7 page7 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 0, 1, 1, 1 d0 d1 d2 d3 d4 d5 d6 d7 1, 0, 0, 0 d0 page8 40 h column address adc d0= "0" seg pin adc d0= "1" 00 01 02 03 04 05 06 07 .............. 83 82 81 80 7f 7e 7d 7c .............. 1 2 3 4 5 6 7 8............... .... .... ...... 01 00 ...... 3f 40 82 83 .... .... ...... 131 132 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 comicn display start com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 an example of common output executing display start from the line address 30 h . com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com64
A31W65132 series preliminary (february, 2001, version 0.1) 23 amic technology, inc lcd drive output waveform (waveform b) the following is an example of how the common and segment drivers may be connected to a lcd panel. v5 v4 v3 v2 v1 vss com 1 v5 v4 v3 v2 v1 vss com 2 v5 v4 v3 v2 v1 vss seg 1 v5 v4 v3 v2 v1 vss seg 2 com 1 - s eg 1 v5 v4 v3 v2 v1 vss -v1 -v2 -v3 -v4 -v5 com 1 - s eg 2 v5 v4 v3 v2 v1 vss -v1 -v2 -v3 -v4 -v5 vdd vss fr cl 1 65 64 2 3 4 5 1 2 3 4 5 1 2 65 64 63 62 61 65 64 63 62 61
A31W65132 series preliminary (february, 2001, version 0.1) 24 amic technology, inc examples of external bias resistor connection vs lcd drive waveform 1/7 or 1/9 bias seg waveform com waveform r a 1 v 5 v 4 v 3 v 2 v 1 v ss r a 1 r a 2 r a 1 r a 1 m m m m g 0 bias r a 1 = r a 1 + r a 1 + r a 2 +r a 1 +r a 1 = 1 g + 4 1 2 ra ra g =
A31W65132 series preliminary (february, 2001, version 0.1) 25 amic technology, inc absolute maximum ratings vss = 0.0v parameter symbol ratings unit supply voltage vdd - 0.4 to +7.0 v lcd drive voltage 1 v5, v out - 0.4 to +18 v lcd drive voltage 2 v1, v2, v3, v4 - 0.4 to v5 v input voltage v in - 0.4 to vdd+0.4 v output voltage v out - 0.4 to vdd+0.4 v operating temperature range topr - 40 to +85 c chip - 55 to +125 storage temperature range tab tstg - 55 to +100 c note 1 stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and th e functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note 2 exposure to absolute maximum rating conditions for extended periods may affect device relia bility. note 3 when connecting a bias resistor externally, set the lcd power supply voltage so that the state is changed to v5 3 vdd.
A31W65132 series preliminary (february, 2001, version 0.1) 26 amic technology, inc dc characteristics unless otherwise specified, vss = 0 v, vdd = 3.0 v 10%, ta = - 40 to 85c rating item symbol condition min. typ. max. units applicable pin operating voltage (1) recom - mended voltage possible operating voltage vdd 2.4 - - - 5.5 - v v vdd* 1 vdd* 1 operating voltage (2) possible operating voltage possible operating voltage possible operatin g voltage v5 v1, v2 v3, v4 (relative to vss) (relative to vss) (relative to vss) 4.5 0 0.6 v5 - - - 16 0.4 v5 v5 v v v v5 v1, v2 v3, v4 high - level input voltage low - level input voltage v ihc v ilc 0.8 vdd vss - - vdd 0.2 vdd v v *3 *3 high - level output voltage low - level output voltage v ohc v olc i oh = - 0.5 ma i ol = 0.5 ma 0.8 vdd vss - - vdd 0.2 vdd v v *4 *4 input leakage current output leakage current i li i lo v in = vdd or vss - 1.0 - 3.0 - - 1.0 3.0 m a m a *5 *5 liquid crystal driver on resistance r on ta = 25 c (relative to vss) v5 = 14.0 v v5 = 8.0 v - - 2.0 3.2 3.5 5.4 k w k w segn comn*7 static consumption current output leakage current i ssq i 5q v5 = 18.0 v (relative to vss) - - 0.01 0.01 5 15 m a m a vss v5 input terminal capacitance c in ta = 2 5 c f = 1 mhz - 5.0 8.0 pf oscillat or frequency internal oscillator external input f osc f cl ta = 2 5 c 18 18 22 22 26 26 khz khz *8 cl supply step - up output voltage circuit v out (absolute value referenced to vss) - - 16.5 v v out voltage regulator circuit operating voltage v out (absolute value referenced to vss) 6 - 16.5 v v out voltage follower circuit operating voltage v5 (absolute value referenced to vss) 4.5 - 16 v v5*9 internal power base voltage v reg0 v reg1 ta = 2 5 c (relative to vss) 0.05%/c 0.2%/c 2.04 4.65 2.10 4.9 2.16 5.15 v v *10 *10
A31W65132 series preliminary (february, 2001, version 0.1) 27 amic technology, inc dc characteristics (continued) . dynamic consumption current (1), during display, with the internal power supply off current consumed by the total ics when an external power supply is used . dynamic consumption current (2), during display, with the internal power supply on ta = 25c rating item symbol condition min. typ. max. units notes vdd=5.0 v, v5=11.0 v - 18 30 vdd=3.0 v, v5=11.0 v - 16 27 vdd=5.0 v, v5=11.0 v - 23 38 i dd (1) vdd=3.0 v, v5=1 1.0 v - 21 35 m a *11 normal mode - 67 112 vdd=5.0v, triple step - up voltage. v5 =11.0 v high - power mode - 114 190 normal mode - 81 135 vdd=3.0v, quad step - up voltage. v5 =11.0 v high - power mode - 138 230 m a *12 normal mode - 81 135 vdd=5.0v, triple st ep - up voltage. v5 =11.0 v high - power mode - 127 212 normal mode - 96 160 A31W65132 i dd (2) vdd=3.0v, quad step - up voltage. v5 =11.0 v high - power mode - 153 255 m a *12 sleep mode i dds1 - - 0.01 5 standby mode i dds2 - - 4 8 m a *13 (consumption current at time of power saver mode, vss=0v, vdd=3.0v 10%) . the relationship between oscillator frequency f osc , display clock frequency f cl and the liquid crystal frame rate frequency f fr item f cl f fr when the internal oscillator circuit is used 4 f osc A31W65132 when the internal oscillator circuit is not used external input 65 x 4 f osc (f fr is the liquid crystal alternating current period, and not the fr signal period.)
A31W65132 series preliminary (february, 2001, version 0.1) 28 amic technology, inc notes: 1. while a broad range of oper ating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the mpu is being accessed. 2. this applies when the external power supply is being used. 3. the a0, d0 to d5, d6 (scl), d7 (si), rd (e), wr (r/ w ), cs1 , cs2, cls, cl, fr, m/s, c68/80, p/s, dof , res , irs, and hpm terminals. 4. the d0 to d7, fr, frs, dof , and cl terminals. 5. the a0, rd (e), wr (r/ w ), cs1 , cs2, cls, m/s, c68/80, p/s, res , irs, and hpm terminals. 6 . applies when the d0 to d5, d6 (scl), d7 (si), cl, fr, and dof terminals are in a high impedance state. 7. these are the resistance values for when a 0.1 v voltage is applied between the output terminal segn or comn and the various pow er supply terminals (v1, v2, v3, and v4). these are specified for the operating voltage (3) range. r on = 0.1 v/d i (where d i is the current that flows when 0.1 v is applied while the power supply is on.) 8. see the relationship between the oscillator freq uency and the frame rate frequency. 9. the v5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. 10. this is the internal voltage reference supply for the v5 voltage regulator circuit. in the A31W65132, the temp erature range can come in three types as vreg options: (1) approximately 0.05%/c (2) 0.2%/c (3) external input. 11., 12. it indicates the current consumed on ics alone when the internal oscillator circuit and display are turned on. the A31W65132 is 1/9 biased. does not include the current due to the lcd panel capacity and wiring capacity. applicable only when there is no access from the mpu. 12. it is the value on a model having the vreg option temperature gradient is 0.05%/c when the v5 voltage regulat or internal resistor is used. 13. when consumption current in power saver mode is measured, the a0, rd (e), wr (r/ w ), d0~d7 terminals must be fixed in h or l.
A31W65132 series preliminary (february, 2001, version 0.1) 29 amic technology, inc timing characteristics system b us read/write characteristics 1 (for the 8080 series mpu) (vdd = 4.5v to 5.5v ta= - 40 to 85 c) rating item signal symbol condition min. max. units address hold time address setup time a0 t ah8 t aw8 0 0 - - ns ns system cycle time a0 t cyc8 166 - ns control l pulse width ( wr ) wr t cclw 30 - ns control l pulse width ( rd ) rd t cclr 70 - ns control h pulse width ( wr ) wr t cch w 30 - ns control h pulse width ( rd ) rd t cchr 30 - ns data setup time d0 to d7 t ds8 30 - ns address hold time t dh8 10 - ns rd access time t acc8 cl = 100pf - 70 ns output disable time t oh8 5 50 ns t aw8 t cchr , t cchw t cyc8 t ah8 t ccr , t cclw t dh8 t acc8 t oh8 t ds8 a0 cs (cs2="1") wr, rd d0 to d7 (write) d0 to d7 (read)
A31W65132 series preliminary (february, 2001, version 0.1) 30 amic technology, inc (vdd = 2.7v to 4.5v ta= - 40 to 85 c) rating item signal symbol condition min. max. units address hold time address setup time a0 t ah8 t aw8 0 0 - - ns ns system cycle time a0 t cyc8 300 - ns control l pulse width ( wr ) wr t cclw 60 - ns control l pulse width ( rd ) rd t cclr 120 - ns control h pulse width ( wr ) wr t cchw 60 - ns control h pulse width ( rd ) rd t cchr 60 - ns data setup time d0 to d7 t ds8 40 - ns address hold time t dh8 15 - ns rd access time t acc8 cl = 100pf - 140 ns output disable time t oh8 10 100 ns (vdd = 2.4v to 2. 7v ta= - 40 to 85 c) rating item signal symbol condition min. max. units address hold time address setup time a0 t ah8 t aw8 0 0 - - ns ns system cycle time a0 t cyc8 1000 - ns control l pulse width ( wr ) wr t cclw 120 - ns control l pulse width ( rd ) rd t cclr 240 - ns control h pulse width ( wr ) wr t cchw 120 - ns control h pulse width ( rd ) rd t cchr 120 - ns data setup time d0 to d7 t ds8 80 - ns address hold time t dh8 30 - ns rd access time t acc8 cl = 100pf - 280 ns output disable time t oh8 10 200 ns notes: 1. the input signal rise time and fall time (t r , t f ) is specified at 15 ns or less. when the system cycle time is extremely fast, (t r + t f ) (t cyc8 - t cclw - t cchw ) for (t r + t f ) (t cyc8 - t cclr - t cchr ) are specified. 2. all timing is specified using 20% and 80% of vdd as the reference. 3. t cclw and t cclr are specified as the overlap between cs1 being ?l? (cs2 = ?h?) and wr and rd being at the ?l? level.
A31W65132 series preliminary (february, 2001, version 0.1) 31 amic technology, inc timing characteristics (continued) system bus read/write characteristics 2 (for the 6800 s eries mpu) (vdd = 4.5v to 5.5v ta= - 40 to 85 c) rating item signal symbol condition min. max. units address hold time address setup time a0 t ah6 t aw6 0 0 - - ns ns system cycle time a0 t cyc6 166 - ns data setup time d0 to d7 t ds6 30 - ns d ata hold time t dh6 10 - ns access time t acc6 cl = 100pf - 70 ns output disable time t oh6 10 50 ns enable h pulse time read write e t ewhr t ewhw 70 30 - - ns ns enable l pulse time read write e t ewlr t ewlw 30 30 - - ns ns t aw6 t ewlr , t ewlw t cyc6 t ah6 t ewhr , t ewhw t dh6 t acc6 t oh6 t ds6 a0 cs1 (cs2="1") e d0 to d7 (write) d0 to d7 (read) r/w
A31W65132 series preliminary (february, 2001, version 0.1) 32 amic technology, inc (vdd = 2.7v to 4.5v ta = - 40 to 85 c) rating item signal symbol condition min. max. units address hold time address setup time a0 t ah6 t aw6 0 0 - - ns ns system cycle time a0 t cyc6 300 - ns data setup time d0 to d7 t ds6 40 - ns data hold time t dh6 15 - ns access t ime t acc6 cl = 100pf - 140 ns output disable time t oh6 10 100 ns enable h pulse time read write e t ewhr t ewhw 120 60 - - ns ns enable l pulse time read write e t ewlr t ewlw 60 60 - - ns ns (vdd = 2.4v to 2.7v ta= - 40 to 85 c) rating item signal symbol c ondition min. max. units address hold time address setup time a0 t ah6 t aw6 0 0 - - ns ns system cycle time a0 t cyc6 1000 - ns data setup time d0 to d7 t ds6 80 - ns data hold time t dh6 30 - ns access time t acc6 cl = 100pf - 280 ns o utput disable time t oh6 10 280 ns enable h pulse time read write e t ewhr t ewhw 240 120 - - ns ns enable l pulse time read write e t ewlr t ewlw 120 120 - - ns ns notes: 1. the input signal rise time and fall time (t r , t f ) is specified at 15 ns or less . when the system cycle time is extremely fast, (t r + t f ) (t cyc 6 - t ewlw - t ewhw ) for (t r + t f ) (t cyc6 - t ewlr - t ewhr ) are specified. 2. all timing is specified using 20% and 80% of vdd as the reference. 3. t ewlw and t ewlr are specified as the overlap between cs1 being ?l? (cs2 = ?h?) a nd e.
A31W65132 series preliminary (february, 2001, version 0.1) 33 amic technology, inc the serial interface (vdd = 4.5v to 5.5v ta= - 40 to 85 c) rating item signal symbol condition min. max. units serial clock period scl "h" pulse width scl "l" pulse width scl t scyc t shw t slw 200 75 75 - - - ns ns ns access setup time a0 t sas 50 - ns address hold time t sah 100 - ns data setup time si t sds 50 - ns data hold time t sdh 50 - ns cs - scl time cs t css t csh 100 100 - - ns ns a0 cs1 (cs2="1") scl si t css t csh t sas t sah t scyc t slw t shw t r tf t sdh t sds
A31W65132 series preliminary (february, 2001, version 0.1) 34 amic technology, inc (vdd = 2.7v to 4.5v ta= - 40 to 85 c) rating item signal symbol condition min. max. units serial clock period scl "h" pulse width scl "l" pulse width scl t scyc t shw t slw 250 100 100 - - - ns ns ns access setup time a0 t sas 150 - ns address hold time t sah 150 - ns data setup time si t sds 100 - ns data hold time t sdh 100 - ns cs - scl time cs t css t csh 150 150 - - ns ns (vdd = 2.4v to 2.7v ta= - 40 to 85 c) rating item signal symbol condition min. max. units serial clock period scl "h" pulse width scl "l" pulse width scl t scyc t shw t slw 400 150 150 - - - ns ns ns access set up time a0 t sas 250 - ns address hold time t sah 250 - ns data setup time si t sds 150 - ns data hold time t sdh 150 - ns cs - scl time cs t css t csh 250 250 - - ns ns notes: 1. the input signal rise and fall time (t r , t f ) are specified at 15ns or less. 2. all timing is specified using 20% and 80% of vdd as the standard.
A31W65132 series preliminary (february, 2001, version 0.1) 35 amic technology, inc display control output timing (vdd = 4.5v to 5.5v ta= - 40 to 85 c) rating item signal symbol condition min. typ. max. units fr delay time fr t dfr c l = 50 pf - 10 40 ns (vdd = 2.7v to 4.5v ta= - 40 to 85 c) rating item signal symbol condition min. typ. max. units fr delay time fr t dfr c l = 50 pf - 20 80 ns (vdd = 2.4v to 2.7v ta= - 40 to 85 c) rating item signal symbol condition min. typ. max. units fr delay time fr t dfr c l = 50 pf - 50 200 ns notes: 1. valid only when the master mode is selected. 2. all timing is based on 20% and 80% of vdd. fr cl (out) t dfr
A31W65132 series preliminary (february, 2001, version 0.1) 36 amic technology, inc reset timing (vdd = 4.5v to 5.5v ta= - 40 to 85 c) rating item signal symbol condition min. typ. max. units r eset time t r - - 0.5 m s reset "l" pulse width res t rw 0.5 - - m s (vdd = 2.7v to 4.5v ta= - 40 to 85 c) rating item signal symbol condition min. typ. max. units reset time t r - - 1 m s reset "l" pulse width res t rw 1 - - m s (vdd = 2.4v to 4.5v ta= - 40 to 85 c) rating item signal symbol condition min. typ. max. units reset time t r - - 1.5 m s reset "l" pulse width res t rw 1.5 - - m s note: all timing is specified with 20% and 80% of vdd as the standard. internal status t rw t r during reset reset complete res
A31W65132 series preliminary (february, 2001, version 0.1) 37 amic technology, inc examples of applications of lcd power supply . when the voltage regulator internal resistor is used. (example 4x step-up) 1. when used all of the step-up circuit, voltage regulating circuit and v/f circuit . when the voltage regulator internal resistor is not used. (example 4x step-up) . when the v5 voltage regulator internal resistor is not used. 2. when the voltage regulator circuit and v/f circuit alone used . when the v5 voltage regulator internal resistor is used. vss c1 vout c3+ c1- c2+ c2- irs m/s vss vdd c1 c1 c1+ c1 v5 v cnt vss vss v3 v4 v5 v2 v1 c2 c2 c2 c2 c2 vss vout c3+ c1- c2+ c2- vss irs m/s vss v3 v4 v5 v2 v1 c1+ v5 v cnt vss c2 c2 c2 c2 c2 vdd external power supply vss vout c3+ c1- c2+ c2- vss irs m/s vss v3 v4 v5 v2 v1 c1+ v5 v cnt vss c2 c2 c2 c2 c2 r3 r2 r1 vdd external power supply vss c1 vout c3+ c1- c2+ c2- vss irs m/s vss v3 v4 v5 v2 v1 c1 c1 c1+ c1 v5 v cnt vss c2 c2 c2 c2 c2 r3 r2 r1 vdd
A31W65132 series preliminary (february, 2001, version 0.1) 38 amic technology, inc examples of applications of lcd power supply (continued) notes: 1. because the vr terminal input impedance is high, use short leads and shielded lines. 2. c1 and c2 are dete rmined by the size of the lcd being driven. select a value that will stabilize the liquid crystal drive voltage. example of the process by which to determine the settings: turn the voltage regulator circuit and voltage follower circuit on and supply a volt age to v out from the outside. determine c2 by displaying a lcd pattern with a heavy load (such as horizontal stripes) and selecting a c2 that stabilizes the liquid crystal drive voltages (v1 to v5). note that all c2 capacitors must have the same capacitanc e value. next turn all the power supplies on and determine c1. 3. when the v/f circuit alone is used 5. when the built-in power circuit is used to drive a liquid crystal panel heavily loaded with ac or dc, it is recommended to connect an external resistor to stabilize potentials of v1, v2, v3 and v4 which are output from the built-in voltage follower. vss vout c3+ c1- c2+ c2- vss irs m/s vss v3 v4 v5 v2 v1 c1+ v5 v cnt vss vdd 4. when the built-in power is not used v2 vss, v0 v4 v5 v3 v1 c2 r4 vss vout c3+ c1- c2+ c2- vss irs m/s vss v3 v4 v5 v2 v1 c1+ v5 v cnt vss c2 c2 c2 c2 c2 external power supply vdd external power supply r4 r4 r4 example of shared reference settings when v5 can vary between 8 and 12v item set value units c1 c2 1.0 to 4.7 0.01 to 1.0 uf uf reference set value r4: 100k ~ 1m it is recommended to set an optimum resistance value r4 taking the liquid crystal display and the drive waveform. w w vss
A31W65132 series preliminary (february, 2001, version 0.1) 39 amic technology, inc connections between lcd drivers (reference examples) the liquid crystal display area can be enlarged with ease through the use of multiple A31W65132 series chips. use a same equipment type. 1. A31W65132 (master) ? ? A31W65132 (slave) the liquid crystal display area can be enlarged with ease through the use of multiple A31W65132 series chips. use a same equipment type, in the composition of these chips. 1. single - chip structure 2. double - chip structure, # 1 A31W65132 master A31W65132 slave m/s vdd m/s fr cl dof output input vss fr cl dof 132 x 65 dots seg A31W65132 master com com 264 x 65 dots seg com seg com A31W65132 slave A31W65132 master
A31W65132 series preliminary (february, 2001, version 0.1) 40 amic technology, inc ordering information part no. package A31W65132c cog A31W65132t tcp

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